SDRAM on the lower ram

[Powervr]

Haha and it worked...
Why? I have some ideas to implement and need to have some type of memory control...
This is with an buffer but will do with an cpld
https://youtu.be/lSKFRrdOxTY

[KWF]

That is nice. Have you used SDRAM or SRAM? Is your of VRAM solution similar to http://sindik.at/data/vram/?

[damik]

Are you sure that you used SDRAM (synchronous dynamic random-access memory) in this project?
And what specific type of SDRAM do you use, SDR or DDR, maybe the newest DDR5?
Refreshing these memories in such a slow system as ZX Spectrum or Timex must have been a problem?
Probably adapting such low-voltage memories to 5V logic may also constitute an additional complication of the circuit.

Perhaps it will make more sense to use SRAM (static random access-memory) there, the solution is much more reliable than constantly using dynamic memories.

[trojacek]

I do not see any SDRAM here, only a Hitachi SRAM 128Kx8.

[damik]

Ok, now I see that there is ordinary SRAM HM628128 and it's even much bigger than you need, because you have 128KB and you only need 16KB, maybe it's better to use 62256 (32KB) and it's still twice as big.

[trojacek]

My guess is the plan is to make the TC2048 compatible with some of Spectrum 128K models. So you'd need 64K of contended memory. And it is much easier to find 128K SRAM chips than 64K ones.

[steev]

And what specific type of SDRAM do you use, SDR or DDR, maybe the newest DDR5?
Refreshing these memories in such a slow system as ZX Spectrum or Timex must have been a problem?

C'mon, DDR5?
Już podłączenie SDR to niezły ból głowy. 
Odświeżanie nie jest problemem, choć trzeba ciut rzeźbić.
Bawiłem się tym na emulowanym specu (spartan6). Jakby to próbować podpiąć pod rzeczywisty sprzęt, to już przez samą konwersję na LVTTL można sobie odpuścić...

[damik]

My guess is the plan is to make the TC2048 compatible with some of Spectrum 128K models. So you'd need 64K of contended memory. And it is much easier to find 128K SRAM chips than 64K ones.

Maybe it's as you write, but let the author himself tell us what the purpose of his action is.

@Steev, a kto ambitnemu zabroni kombinować, to bardziej byłaby sztuka dla własnej satysfakcji niż coś optymalnie sensownego.

[KWF]

@Powervr: so you use an ordinary 128K SRAM. What portion 128K do you use in your design? is it 16K, 32K or 64K chunk?

Could you share the schematic diagram, please?

[Powervr]

Sorry for the late replay...
Indeed not SDRAM but indeed SRAM, on my head I thought it was SDRAM hahaha ! even without knowing much about ram, I was able to build this for the lower ram.

My mistake it's SRAM indeed. 

The idea is just to start and play with this, the problem is I don't want to use original timex for this "playing" around, they are too much valuable for me. so Will build a timmy to play around, and yes, the idea  is to make possible stuff like the other screen on 128k, but not only that... I have some ideas... will  post the evolution  on the stuff... next an CPLD... instead of the buffer and the not logic.

[Powervr]

@Powervr: so you use an ordinary 128K SRAM. What portion 128K do you use in your design? is it 16K, 32K or 64K chunk?

Could you share the schematic diagram, please?

Will do it! there is some weird stuff that I am unable to reproduce after I removed  the wires...  (because the pcb didn't work), have to make the cpld with this SRAM... when I made it Will give it to everyone.

I broked my future was 8 bit divmmc... with me playing around... Had to build another divmmc dos tiesos. (less expensive) https://github.com/mcleod-ideafix/divtiesus
now that I have again an working Divmmc will do it.

I have several pcb's for an xilinx and the sram. not yet soldered or programmed it, will do it!
I do not know much about electronic, or VHDL, but I love to explore...
And obviously I will  learn walking.

[Powervr]

schematics view

I am not using the cpld here, was able to put this to work with the pcb, an tri state buffer, the hitachi sram, and a not gate. for the RAS signal ... the buffer uses the signal at the clock not at the optimal moment. See the link to the zx spectrum ram that I post bellow.

[Powervr]

it boots faster... no  problem ...But you need to find smaller equivalents this doesn't fit, it was just to see if an asynchronous sram would be feasible.... the signal IS much better this goes from 0 to 5v and vice versa much quicker. 
the signal is cleaner... works like an champ!

[Powervr]

I took my ideas from here:

https://sindik.at/data/vram/?fbclid=IwAR1gLlYL7GWgI9SXZYXVUeDLCp8qJh_vkeUkO6hSmA_G05svdAuRt9EwC6w
 I Just changed some  stuff to get it to work

the only thing that you need to know is. A8 and A15 should be put to 5V or ground in the collumn (when/CAS active) there is only 6 adress bits (that is for the lower 16k bit memory... this is overkill... but I have many memories.. I can think  an way with  an cpld and clock to get it to work  alone for the entire bank... or even to give 128. next.
this is the A0 and A7  of the collumns  when /CAS is active.

In the row there is all 8 bits, that went before to the tri-state buffer

there is no problem if you change the adress lines, that is  A0 to A3 A3 to A0... or even the data lines...
But the A8 and  A15 of the /CAS active should be put to  ground ot 5V it will not work I tried
look At the pins on my schematics

Remember this doesn't fit, but works... next time I will make an smaller pcb and chips not socketed... to get this

U4 and U1 is just the sockets for the place of the older ram  that need to be well placed ... to fit

[Powervr]

I will make an video to show you it boot at half the time. hahaha

https://youtu.be/aM32GOVUTTc?feature=shared